The CPU internal registers clear, and the instruction pointer is hardwired to look at a specific logical address known as the Reset Vector (typically located at address 0xFFFFFFF0 ).
The BIOS initiates the POST routine, checking system components sequentially: CPU Internal Registers System RAM (Memory training takes place here) Graphics Adapter (GPU initialization) Storage Drives and Peripherals
With the primary PSU rails active, the motherboard's localized buck regulators take over to power specialized high-draw components.
Individual motherboard buck controllers chain their individual PG signals together. desktop motherboard power sequence pdf exclusive
Typically 1.2V to 1.8V is generated first, as the CPU needs stable memory to begin execution. PCH/Chipset Rails:
Troubleshooting boot failures often means tracing the power sequence to find the missing step. Below are systematic approaches for common scenarios.
3. System Agent Power: The motherboard VRM (Voltage Regulator Module) generates VCCSA and VCCIO . 4. CPU VCore Generation: The PWM Controller for the CPU wakes up. * It generates the VCORE (CPU Core Voltage). * It generates VTT (DDR Voltage) . The CPU internal registers clear, and the instruction
The PCH releases "Sleep" signals ( SLP_S5# , SLP_S4# , SLP_S3# ). Once these go "High," the motherboard enters the "Wake" state.
The final stage of the hardware power sequence focuses entirely on preparing the central processing unit (CPU) to execute code.
SIO pulls the Green wire (PS_ON) to Ground, activating all main rails (+12V, +5V, +3.3V). Typically 1
| | Description | Access Level | |--------------|-----------------|------------------| | ATX Specification 2.x/3.x | Defines PSON#, PWR_OK timing, +5VSB requirements | Public | | Intel PCH Datasheet | Rail definitions, sequencing tables, SLP_Sx signals | NDA (some public excerpts) | | Intel EC Firmware Power Sequencing Module | EC handling of G3→S0 transitions and RSMRST# generation | Public (via GitHub) | | AMD Fusion Controller Hub Documentation | AMD-specific rail sequencing tables | Public summaries available | | Processor Power Sequencing Signals | Detailed PROCPWRGD, VCCST_PWRGD definitions | Public (Intel EDC) |
The Super I/O and VRM controller verify that local motherboard voltages (VCORE, VDDQ) are stable. If everything is perfect, the Super I/O generates SYS_PWROK and sends it to the PCH. 2. Clock Generator Initialization
The Super I/O pulls the PSU's Green wire to Ground. This tells the PSU to turn on all main voltage rails (+12V, +5V, +3.3V). Phase 3: The Power-OK Logic
The CMOS battery maintains the Real-Time Clock (RTC) and BIOS settings.
The SIO chip pulls the green wire ( PS-ON# ) of the ATX connector to ground, telling the PSU to turn on all main rails (12V, 5V, 3.3V). Phase 3: Hardware Initialization